1. Field of the Invention
The present invention relates to an electrostatic-breakdown-preventive and protective circuit for a semiconductor-device separately provided with a dedicated power-source line and a dedicated ground line for driving an output transistor and a dedicated power-source line and a dedicated ground line for a logic circuit.
2. Description of the Related Art
In recent years, a semiconductor integrated circuit (may be hereinafter referred to as a semiconductor device or a device) uses a power-source line for driving an output transistor (hereinafter as output power-source line) and a power-source line for operating a logic circuit (hereinafter referred to as internal power-source line) by separating them from each other. This is because if they are used together, the voltage of the power-source line drops when the output transistor is turned on and a large current flows and the voltage drop is directly transmitted to the power-source line of the logic circuit and thereby, the logic circuit may not operate normally. In the case of this semiconductor device, ground lines are usually separated into a ground line for driving the output transistor (hereinafter referred to as output ground line) and a ground line for operating the logic circuit (hereinafter referred to as internal ground line). This type of device has a problem of an electrostatic breakdown easily occurring therein. The reason for this problem is described below by using an input/output terminal as an example.
FIG. 12 shows a conventional semiconductor-device electrostatic-breakdown-preventive and protective circuit (circuit diagram of an input/output terminal). A P-channel MOS (Metal-Oxide-Semiconductor, hereinafter referred to as PMOS) output transistor 102 is connected between an input/output line 101 and an output power-source line 110 and an N-channel MOS (Metal-Oxide-Semiconductor, hereinafter referred to as NMOS) output transistor 103 is connected between the input/output line 101 and an output ground line 120. The input/output line 101 is connected to gates of a PMOS transistor 105 and an NMOS transistor of an inverter 130 constituted by the PMOS 105 and NMOS 106 through a protective resistor 104. The source of the PMOS transistor 105 is connected to an internal power-source line 111 and the source of the NMOS 106 is connected to an internal ground line 121. The drain of the PMOS 105 and the drain of the NMOS 106 are shorted. In the case of the above input/output circuit, when an electrostatic surge is applied between the input/output line 101 and output power-source line 110, the PMOS output transistor 102 serves as a protective transistor. That is, because a surge current passes through the PMOS output transistor 102 serving as both an output transistor and a protective transistor, the gates (oxide films) of the PMOS transistor 105 and the NMOS transistor 106 of the inverter 130 are not easily broken down (hereinafter, PMOS output transistor is referred to as PMOS protective transistor 102). The protective resistor 104 prevents a surge voltage from being transitionally applied to the gates of the PMOS transistor 105 and the NMOS transistor 106 of the inverter 130 until the surge current completely passes through the PMOS protective transistor 102. Also when an electrostatic surge is applied between the input/output line 101 and the output ground line 120, gates of the PMOS transistor 105 and the NMOS transistor 106 of the inverter 130 are not broken down because a surge current passes through the NMOS output transistor 103. Because the NMOS output transistor 103 also serves as both an output transistor and a protective transistor, it is hereinafter referred to as an NMOS protective transistor 103.
However, when an electrostatic surge is applied between the input/output line 101 and the internal power-source line 111, the gate of the PMOS transistor 105 of the inverter is easily broken down because there is no route for passing a surge current. Similarly, when an electrostatic surge is applied between the input/output line 101 and internal ground line 121, the gate of the NMOS transistor 106 of the inverter 130 is broken down.
To solve the above problems, an improved protective transistor, shown in FIG. 13, is used. That is, a PMOS protective transistor 107 is provided between the output power-source line 110 and the internal power-source line 111 and an NMOS protective transistor 108 is provided between the output ground line 120 and the internal ground line 121. By providing the PMOS protective transistor 107, even if an electrostatic surge is applied between the input/output line 101 and the internal power-source line 111, a surge current passes through the PMOS transistor 102 and the PMOS transistor 107. Therefore, it is possible to prevent the gate of the PMOS transistor 105 of the inverter 130 from being broken down. Even if an electrostatic surge is applied between the input/output line 101 and internal ground line 121, because a surge current passes through the NMOS protective transistors 103 and 108, it is possible to prevent the gate of the NMOS transistor 106 of the inverter 130 from being broken down.
In the case of the above method, however, the area of a protective transistor is generally increased because it is necessary to secure response characteristics of the PMOS protective transistor 107 and the NMOS protective transistor 108 to an electrostatic surge. Moreover, in the case of this method, because a surge current passes through two devices such as the PMOS protective transistors 102 and 107 or the NMOS protective transistors 103 and 108, it is necessary to increase the resistance value of the protective resistor 104 so that a surge voltage is not applied to gates of the PMOS transistor 105 and the NMOS transistor 106 of the inverter 130 by the time the surge current completely passes between the two devices. Because increase of the PMOS protective transistor 107 and the NMOS protective transistor 108 in size causes the area occupied by a protective device to increase, there are disadvantages that the number of restrictions on a pattern layout increases and the chip cost is increased and increase of the resistance value of the protective resistor 104 is disadvantageous for high-speed operations.